DPA-resistant QDI dual-rail AES S-Box based on power-balanced weak-conditioned half-buffer
James Lim, Weng‐Geng Ho, Kwen‐Siong Chong, Bah‐Hwee Gwee · 2017
We propose an asynchronous-logic (async) Quasi-Delay-lnsensitive (QDI) dual-rail 32-bit Advanced Encryption Standard (AES) Substitution-Box (S-Box) for Differential Power Analysis (DPA) attack countermeasure. There are three novel features in the proposed S-Box. First, the proposed S-Box operates in async QDl protocol with dual-rail data encoding, hence there is only a marginal difference in power dissipation for different signal output transitions. Second, the proposed S-Box embodies the power-balanced async Weak-Conditioned Half-Buffer (WCHB) cell approach, which features the same number of transitions, and hence same number of switching for different input combinations to equalize the power dissipation. Third, the proposed S-Box embodies our novel-designed library cells in which each output wire, corresponding to different transitions, has a similar capacitive load, hence hiding the dynamic power dissipation. Based on the 65nm CMOS process, we implement the proposed 32-bit AES S-Box, and benchmark it against the conventional synchronous-logic (sync) S-Box and the reported async (i.e. unbalanced) WCHB S-Box. From the simulation results, our proposed power-balanced WCHB S-Box features significantly lower 1.21% and 0.55% of Normalized Energy Deviation (NED) and Normalized Standard Deviation (NSD) respectively. Particularly, our proposed design is of 57.6× and 17.9× lower NED, and 55.1× and 9.29× lower NSD than the reported sync and async counterparts respectively.