FPGA implementation of combined S-Box and InvS-Box of AES
M. Rajeswara Rao, Ramesh K. Sharma · 2017
An implementation of a combinational memory-less S-Box and invS-Box (combinely) for ByteSub and InvByteSub transformations of AES on a same hardware. This is a part of the combined architecture of AES in which both encryption and decryption can be performed with an enable pin. Previously LUTs are used to implement the S-Box and InvS-Box of AES separately, which causes large amount of memory and area. In this paper, the proposed architecture is implementing using composite field arithmetic in finite fields GF(28) which is advantageous than LUT approach on the basis of hardware complexity. As both S-Box and InvS-Box are implementing on a same hardware, there is large reduction in gate count as well as in area. The power consumption is also reduced because of the resource sharing of multiplicative inverse module in both S-Box and InvS-Box. The proposed architecture implemented on Atrix7 FPGA board using Verilog HDL in Xilinx ISE 14.7.