Test point insertion for RSFQ circuits
Gleb Krylov, Eby G. Friedman · 2017
A test point insertion technique for enhanced testability in superconductive RSFQ logic is proposed here. Test point insertion reduces the overhead of a set/scan chain while maintaining most of the functionality. The SFQ multiplexers are replaced with mergers and blocking gates. The multiplexer control signals are replaced with a gated clock signal. Clocked blocking gates are used to disable undesired data input. The proposed technique requires 35% fewer Josephson junctions as compared to multiplexers when applied to a 64-bit register. This technique can be utilized to evaluate error prone SFQ circuits and for built-in self-test of SFQ compatible memory systems.