A flexible multi-core functional cache simulator (FM-SIM)
Rano Mal, Yul Chu · 2017
This paper presents a flexible multi-core functional cache memory simulator to design and evaluate memory hierarchies for modern general-purpose or embedded processors. The proposed simulator needs to work with Pin, which is an open-source dynamic instrumentation tool provided by Intel. The Pin intercepts the execution of instructions and generates a sequence code (traces) to feed into the simulator for any selected benchmark programs, such as SPEC2006, SPLASH2, or PARSEC. We have a plan to release this simulator as an open-source (like Pin) to support research and/or academic community for their purpose. In addition, we expect more functions can be updated on top of this simulator to share by the research community.