Acceleration Techniques for System-Hyper-Pipelined Soft-Processors on FPGAs
Tobias Strauch · 2017
A promising technique to improve the performance per area factor for multithreaded soft-processors on FPGAs is System Hyper Pipelining (SHP), which can be efficiently applied on the register rich reconfigurable technologies with their distributed memory structures. SHP overcomes the limitations of C-Slow Retiming by adding context switching to enable thread stalling and thread bypassing possibilities. This enables thread reordering and dynamic thread scheduling techniques. The paper concentrates on acceleration techniques to improve the performance of an individual thread of a SHP based multithreaded CPU. This can be done by combining SHP with concepts such as cycle scaling, deep pipelining and out-of-order execution. The given results based on a Cortex M3 CPU mapped on a Virtex-6 FPGA are very promising.