FPGA implementation of Gram-Schmidt QR decomposition using high level synthesis
Parth Desai, Semih Aslan, Jafar Saniie · 2017
In this paper, a high precision QR decomposition implementation on FPGA is discussed. The Gram-Schmidt algorithm is used and synthesized from high level language to Register Transfer Level (RTL) Verilog HDL, using High Level Synthesis (HLS). The RTL Code is synthesized and implemented on Xilinx Zedboard FPGA. The IP core that is generated during simulation is designed for 10×10 floating point and fixed point implementation which can be scaled up for higher matrix sizes. The results for scaled up 100×100 matrix implementation are also discussed. Fixed point data type provides twice as fast implementation and consumes nearly 30% less area compared to floating point implementation with no more than 3% error in precision, for 10×10 matrix size. The error percentage would vary with the size of matrix as well.