Interleaved logic-in-memory architecture for energy-efficient fine-grained data processing
Kai Yang, Robert Karam, Swarup Bhunia · 2017
For a growing pool of data-intensive applications, data transfer, rather than processing speed, has emerged as the major bottleneck to performance and energy scalability. In this paper, we propose a novel interleaved logic-in-memory architecture, referred to as MISK, which leverages fine-grained integration of logic functions within dense, 2-D static random-access memory (SRAM) arrays for in-situ information processing. We have custom designed a complete MISK fabric using Cadence physical design toolsets, and simulated a set of nine application kernels to evaluate the effectiveness and scalability of the approach. Results are compared to an unmodified OpenRISC CPU, demonstrating an average 1.9× latency reduction and 1.6x increase in energy efficiency, while contributing only 9% additional area overhead compared to a MISK-free CPU.