A Codec, tiles to NoC router interface, for next generation FPGAs with embedded NoCs
Alaa Salaheldin, Hassan Mostafa, Ahmed M. Soliman · 2017
Nowadays, SoC uses Network on Chip (NoC) to connect its increasing number of building blocks. FPGAs, like SoCs, can use NoC to connect its increasing number of tiles, memories, DSP slices and embedded processors. But one drawback of using NoC is that increasing its router ports will affect the area, power and frequency of the system significantly. For FPGAs to benefit from the NoC approach we have to find a way how to interface with large number of blocks without increasing NoC router ports. In this paper we use a concentrator module or a Codec to connect between routers and multiple Tiles (FPGA basic building block). Using this codec will reduce the effect of increasing tile count on the area, power and frequency of the FPGA routing network. A 64-tiles network with codec would consume less than 15% area, less than 50% power of a NoC-only network and operates with 2.5X frequency.