Formal modeling and verification for pre-charge half buffer gates and circuits
Ashiq A. Sakib, Scott C. Smith, Sudarshan K. Srinivasan · 2017
A formal modeling and verification methodology for Pre-Charge Half Buffer (PCHB) gates and circuits is presented. PCHB gates have hysteresis and incorporate a handshaking protocol. Thus, we model gates as transition systems and provide correctness property templates that capture safety and liveness. The methodology is demonstrated using several circuits.