Expanding the un-usable area strategy for improved utilization of reconfigurable FPGAs
Godwin Enemali, Adewale Adetomi, Tughrul Arslan · 2017
The addition of hard blocks such as Block RAMs and Digital Signal Processors, have proven to be good means of improving various performance metrics in FPGAs. This however places stricter constraints on runtime relocation of hardware tasks and hence reduces their application in dealing with permanent faults. In this paper, we present a strategy that enhances the utilization of heterogeneous reconfigurable FPGAs by minimizing resources which are tied down as unusable areas. Our results show that the strategy leads to a 9.4% reduction in task rejections and improved placement quality compared to state of the art techniques. The complete implementation occupies only 1712 LUTs and 1645 Flip Flops on the Xilinx's xc7z100ffg900-2. Based on this strategy, more task relocations can be obtained which enhances the capacity of FPGAs to deal with permanent faults.