A high-performance FPGA-based LDPC decoder for solid-state drives
Yanhuan Liu, Chun Zhang, Pengcheng Song, Hanjun Jiang · 2017
In order to improve the throughput of error correction decoding for the high-performance solid-state drives (SSDs), a semi-parallel low-density parity-check (LDPC) decoding architecture is proposed in this paper. The circuit of the LDPC decoder which can be dynamically configured with bit rate and code length is implemented using the scheduling control flow mode of single instruction multiple data (SIMD) instruction. The Peripheral Component Interconnect Express (PCIe) interface is designed and the adaptive normalization factor is applied to achieve an average improvement of 35% in throughput with a signal-to-noise ratio (SNR) of 6.08 dB. The LDPC decoder is implemented on the Xilinx VC709 FPGA. With a rate-0.94 length-35840 quasi-cyclic LDPC code, the decoder achieves a throughput of 1.97 Gb/s which compares favorably with previously proposed architectures.