A low power AES-GCM authenticated encryption core in 65nm SOTB CMOS process
Van‐Phuc Hoang, Van-Tinh Nguyen, Anh-Thai Nguyen, Cong‐Kha Pham · 2017
This paper presents a low power AES-GCM authenticated encryption IP core which combines an improved four-parallel architecture, an advanced 65nm SOTB CMOS technology and a low complexity clock gating technique. As a result, the power consumption of the proposed AES-GCM core is only 8.9mW which is lower than other AES-GCM IP cores presented in literature. The detail implementation results are also presented and discussed.