A secure test solution for sensor nodes containing crypto-cores
Shoaleh Hashemi Namin, Ankit Mehta, Parham Hosseinzadeh Namin, Rashid Rashidzadeh, Majid Ahmadi · 2017
There is a tradeoff between the requirements for security and testability for a sensor node hardware. To test a sensor, it is desired to have access to the internal circuitry of the Device-Under-Test (DUT) to apply test stimuli and observe its responses. While such unrestricted access to the DUT is desired for testing, it can undermine the security. To secure a sensor node from attacks by malicious attackers, it is imperative to limit user access once the device has been adopted for in-field use. Efficient design-for-testability (DFT) techniques have been developed without taking into consideration the security threats posed by them. For instance, scan structure which is widely deployed in modern digital circuits, can be used as an effective tool to wage an attack and extract critical information from cryptographic cores. In this work, a new solution is presented to protect sensor nodes containing crypto-cores against scan-based attacks without compromising their testability at the manufacturing phase. In the proposed solution, a built-in self-test (BIST) technique is developed to carry out in-field tests for crypto-cores while a scan-based test method is utilized for manufacturing test. The proposed method prevents scan-based attacks without compromising testability during the manufacturing phase.