Self-Adaptive Timing Repair
Hans Giesen, Raphael Rubin, Benjamin Gojman, André M. DeHon · IEEE Design and Test · 2017
This article describes a method to continuously monitor paths delays in an operational FPGA design and to improve slow paths by incremental partial reconfiguration. Since online delay measuring is more accurate than design time estimation, this approach allows to balance delays which can be used to improve performance or reduce power consumption. In addition, it counteracts aging effects and prolongs the system’s useful life time.—Axel Jantsch, TU Wien