Ultra-high-speed and universal-coding-rate Viterbi decoder VLSIC - SNUFEC VLSI
Katsuhiko Kawazoe, S. Honda, Shuji Kubota, Shuzo Kato · IEICE Transactions on Electronics · 1994
An ultra-high-speed (higher than 60 Mb/s) Viterbi decoder VLSIC with coding rates from one-half to fifteen-sixteenths and a constant length of seven for forward error correction (FEC) is developed using 0.8-/spl mu/m semi-custom CMOS LSIC technology. To reduce the power consumption of the one-chip high-coding-rate Viterbi decoder, a newly developed universal-coding-rate scarce-state-transition (SST) Viterbi decoding scheme and low-power-consumption burst-mode-selection (BMS) path memory are employed. A new maximum-likelihood-decision, (MLD) circuit for the SST Viterbi decoder is developed to reduce the path memory length without coding-gain degradation. The developed Viterbi decoder VLSIC achieves a maximum data rate of 60 Mb/s with a power consumption of 2.5 W and achieves near theoretical net coding-gain performance for various coding rates. >