A Design and Performance Evaluation of Dynamically Self-Reconfigurable System Based on Virtex5
Liang Zhang, Peiyi Shen, Yuxin Cai, Jingwen Liu, Juan Song · Advances in intelligent systems research/Advances in Intelligent Systems Research · 2015
Facing with limitation of hardware resources and increasingly requirements of processing ability, reconfigurable computing technology has become an inevitable trend in compute-intensive system.Dynamic and Partial Reconfiguration (DPR) is a special feature embedded in Field Programmable Gate Arrays (FPGAs), giving designer the ability to reconfigure a certain portion of the FPGA during run-time without influencing the other parts.This paper makes an analysis of time consumption of FPGA-based dynamic reconfiguration and proposes a piecewise reconfigurable system time-consuming model for Xilinx Virtex-5, and then analyzes and obtains the time-consuming parameters of each stage.In addition, an entire time-consuming calculation formula of reconfiguration process is introduced by combining all stages formulas.The experiments results indicate that calculation formula error rate of the reconfiguration time-consuming model is less than 10%, and which can verify the accuracy of the formula.