A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory
Chulbum Kim, Doo-Hyun Kim, Woopyo Jeong, Hyunjin Kim, Il Han Park, Hyunwook Park, JongHoon Lee, Jiyoon Park, Yang-Lo Ahn, Ji Young Lee, Seungbum Kim, Hyun-Jun Yoon, Jae Doeg Yu, Na-Young Choi, NaHyun Kim, Hwajun Jang, Jong-Hoon Park, Seung-Hwan Song, Yongha Park, Jinbae Bang · IEEE Journal of Solid-State Circuits · 2017
A 64-word-line-stacked 512-Gb 3-b/cell 3-D NAND flash memory is presented. After briefly examining the challenges that occur to a stack, several technologies are suggested to resolve the issues. For performance enhancement, a novel program method hiding two-page data loading time is presented. This paper also discusses an electrical annealing improving reliability characteristic by removing holes in shallow traps. In addition, a valley tracking read for reducing timing overhead at a read retry is introduced by fast finding optimal read levels. Finally, a high-speed self-test mode for IO operation is presented. The chip, designed with the fourth generation of V-NAND technology, achieved an areal density of 3.98 Gb/mm2and operated up to 1 Gb/s at 1.2 V.