Design of low power memory architecture using 4T content addressable memory cell
Pasula Ramakrishna, S. Rajendar, Nagarjuna Malladhi · 2017
In this paper, a novel low power 4T content addressable memory (CAM) cell based Master-Slave Match Line (MSML) design for memory architectures is proposed. In memory architectures, match lines (MLs) and search lines (SLs) are main sources of power consumption. The proposed 4T CAM cell based MSML design reduces the area by 25%, delay by 11%-30% and total power consumption by 62% compared with 6T CAM cell based MSML design.