A reusable verification environment for NoC platforms using UVM
Ahmed S. Eissa, Moamen A. Ibrahem, Mahmoud A. Elmohr, Yasmin Zamzam, Ahmed El-Yamany, Sameh El-Ashry, Mostafa Khamis, Ahmed Shalaby · 2017
Network on Chip (NoC) has emerged as an interconnection solution for the modern digital systems, especially for System on Chip (SoC), due to the large number of IPs in the system that need to communicate. Various systems and routers have been introduced; hence the need to make a reusable verification environment to test both single routers and networks. In this paper, we propose a reusable verification environment for NoC platforms using the Universal Verification Methodology (UVM) that tests and verifies both routers and networks in an easily modifiable manner to fit various routers and networks. The environment also evaluates performance parameters such as injection rate, throughput and latency.