Design and Simulation of a Charge-Pump Phase-Locked Loop in 65 nm CMOS Technology
Ashwarya Rajwardan · Illinois Digital Environment for Access to Learning and Scholarship (University of Illinois at Urbana-Champaign) · 2016
This thesis gives a brief overview of a basic PLL circuit and reports the in-depth analysis of the design procedure and working of a charge-pump phase-locked loop (PLL) in 65 nm CMOS technology. The design is done for a target output frequency of 1.2 GHz and the goal is to use it in a transmitter block of a high-speed serial link (HSSL). A thorough discussion of simulation results with phase noise and jitter results using circuit simulation tool follows the analysis.