Dynamic Partial Self-Reconfiguration of FPGAs for Digital Broadcasting Receiver Systems
Michael Feilen · 2017
The main contribution of this work is the analysis of techniques for the design of resource-efficient broadcasting receiver systems using dynamically and partially reconfigurable field-programmable gate arrays. The research covers concepts for resource-sharing and resource time-multiplexing of receiver processing elements on partially-reconfigurable platforms with a focus on practical applicability. As a result, recommendations are provided for the design of novel receiver architectures using self-reconfigurable field-programmable gate arrays.