A VLSI Based Systolic Architecture For Fast Gaussian Convolution
A . Giordano, Massimo Maresca, Giulio Sandini, T. Vernazza · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1985
The paper deals with an algorithm driven architecture devoted to fast edge detection. The architecture has been specifically designed to process large convolution masks in a pyramidal (multiresolution) scheme. The basic element of the convolution board is a pro-grammable VLSI component. Several identical components can be connected in a virtually systolic structure in order to achieve the desired throughput rate. A distinctive feature of the system is the multiple-resolution capability of the convolver board. The number of convolver boards hosted by a multiple bus vision machine can be selected to achieve a parallel multiple-resolution operation. The main application of the proposed architecture is for fast edge detection based on the extraction of the zero-crossings of Gaussian filtered images. The paper is divided into two sections: In the first one results of numerical simulations are presented showing the accuracy of this edge detection technique applied on convolved images in a pyramidal structure while in the second, one the systolic architecture implementing the algorithm is presented.