A 40nm split gate embedded flash macro with flexible 2-in-1 architecture, code memory with 140MHz read speed and data memory with 1M cycles endurance
Hung-Chang Yu, Ku-Feng Lin, Yu-Der Chih, Jonathan Chang · 2017
This paper presents a 40nm 9.5Mb embedded flash (eflash) macro which can be partitioned as code storage and data storage in a single macro with enhanced read margin by using two design schemes: temperature adaptive reference scheme and flexible array partitioned scheme. By way of these design features, code storage memory achieves 140MHz read speed at the junction temperature of 160°C and data storage memory achieves 1M cycles endurance.