System architecture with single chip 8K HEVC decoder for 8K advanced BS receiver system
Masaitsu Nakajima, Daisuke Murakami, Hironori Kubo, Takahide Baba, Y. Miki · 2017
To implement 8K Advanced BS receiver system, 8K HEVC decoder SoC is developed as key component. To solve the exceeded required memory bandwidth over physical memory bandwidth limitation issue for realizing 8K decoder, two types of multi-cast write back scheme, including reference data multi-cast write back and output data multi-cast write back, are introduced. 8K HEVC decoder chip is fabricated in 28nm CMOS technology and SIP packaged with eight DDR3 memories.