An architecture for a rational arithmetic unit
David Matula, Shrikant N. Parikh · 1988
Previous research on finite precision rational arithmetic is surveyed. The goal of developing an architecture for rational arithmetic based on the extended Euclidean algorithm is described. Arguments and results of the proposed unit are floating slash fractions with rounding effected by the classical number theoretic concept of best rational approximation. A nonrestoring redundant binary Euclidean algorithm is developed to drive the arithmetic unit. The algorithmic efficiency of the unit is shown to be competitive with floating point division in terms of number of shifts and add/sub operations. A coprocessor architecture for this rational arithmetic unit is described which allows user specifiable precision and range comparable to standard floating point systems. The architecture is tested by developing a VLSI model and verifying execution times comparable to coprocessor divide times on the intel8087 and NS32081.