A 2.267 Gbps, 93.7pJ/b non-binary LDPC decoder for storage applications
Yuta Toriyama, Dejan M. Markovic · 2017
This paper presents a Non-Binary LDPC decoder with information throughput of 2.267Gbps and power consumption of 212.4mW, yielding an energy efficiency of 93.7pJ/b, implemented in a 40nm CMOS technology. The employed code is long and high-rate without degree-2 variable nodes, resulting in a low error floor. A dual decoding algorithm scheme alleviates the computational complexity of decoding, realized in an efficient architecture with high parallelism and avoidance of idle clock cycles.