Encoding of chain outputs in FPGA-based Moore FSMs
Alexander A. Barkalov, Larysa Titarenko, Jacek Bieganowski · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2017
A method of hardware reduction is proposed for logic circuits of Moore FSMs implemented with FPGAs. The method is based on replacement of the state register by a state counter. The specific of the proposed method is that the counter content is incremented for unconditional and conditional transitions. An example of application of proposed method is given.