Design and Implementation of a Virtual Hardware Machine
Sebastian Lange · Publikation Server (Leipzig University) · 2003
Reconfigurable hardware will be used in many future embedded applications. Since most of these embedded systems will be temporarily or permanently connected to a network, the possibility to reload parts of the application at run time arises. Current reconfigurable devices use FPGAs to implement changing functionality. FPGAs themselves, prove to be inherently incompatible to each other. This leads to tremendous number of configuration binaries for the same hardware design. The Java approach, based on a Java Virtual Machine (JVM), was invented to solve the problem for software. This thesis presents a way of implementing the hardware parts of an embedded system using a hardware byte code, which can be interpreted by a virtual hardware machine running on an arbitrary FPGA. Within this work the Virtual Hardware Byte Code was defined and a simulation environment for the Virtual Hardware Machine, as well as a VHDL to byte code compiler have been implemented. Using these tools the byte code and the machine was tested for validity of the approach. The results show that this approach is feasible and that it leads to fast and portable reconfigurable designs, which run on any programmable target architecture.