Cache coherence for scalable shared memory multiprocessors
Manu Thapar · 1992
Shared memory multiprocessors have become an important form of computer systems. Such systems have multiple processors, each of which can access the shared main memory in the system. If each processor has an associated cache, copies of the same data may be present in multiple caches at the same time. This results in the important cache coherence problem, namely, when a processor writes to the data, the multiple copies need to be kept consistent. In this thesis we present some solutions to the cache coherence problem and discuss their advantages and disadvantages. A new Singly-linked Distributed Directory (SDD) cache coherence protocol is presented. The SDD protocol uses a linked list of cache lines that contain shared copies of the data to maintain coherence. The protocol has scalable cost. The protocol does not require coherency related messages to be delivered in order, and thus allows adaptive routing, making the performance more robust in the presence of congested networks. We have defined an efficient implementation of locks that integrates well with the cache coherence protocol. We compare the performance of the SDD protocol with a fully mapped centralized directory protocol and the IEEE SCI Standard protocol. The SDD protocol has generally lower interconnect traffic than the other two protocols. Our analysis shows that the SDD protocol has better performance in the presence of memory and interconnect contention. The serial invalidations used by the SDD protocol have been included as part of the optimizations of the SCI protocol in order to reduce the interconnect traffic for invalidations. We discuss the various factors, such as memory reference behavior and interconnect traffic, that affect the performance of these protocols. The cost and performance benefits of the SDD protocol make it a viable solution to the cache coherence problem in large scale shared memory multiprocessors.