An efficient method for testing multipliers of embedded DSPs in FPGA
Zhiqian Zhang, Jinmei Lai · 2016
This paper presents an efficient method to generate BIST scheme for multipliers of embedded DSPs in an FPGA. It not only can be applied to those multipliers consisting of half adders and full adders but also some complex multiplier circuits with other compressors. This approach provides an easy way to generate test set for target multipliers. We apply our method to different multipliers with different input bit-widths, coding circuits and compress circuits and achieve high fault coverage with a small number of test configurations. It only needs 213test vectors to test a 18×18 Booth2 multiplier with complex Wallace tree structure and reaches fault coverage greater than 99%.