A low-complexity FFT Processor using two-dimensional algebraic integer encoding
Sangho Yun, Fan Wu, Gerald E. Sobelman, Xiaofang Zhou · 2016
An efficient architecture of a 64-point FFT processor using two-dimensional algebraic integer (AI) encoding is presented. The advantage of two-dimensional AI encoding is that the hardware complexity for multiplication is reduced since a multiplication can be replaced by a few simple shifts and additions. The ROMless FFT processor, which replaces the ROM for twiddle factors with a twiddle factor generator (TFG) using 2-D AI encoding, has less hardware complexity than previous implementations. The proposed architecture uses a wordlength of 14 bits to achieve an acceptable SNR. It has been synthesized onto an FPGA, and comparative resource utilization results are presented.