VLSI design of an ultra-high-speed Polar encoder architecture using 16-parallel radix-2 processing engines for next-generation 5G applications
Xin-Yu Shih, Po‐Chun Huang · 2017
This paper presents an ultra-high-speed/area-efficient Polar encoder design with very high system throughput for emerging next-generation 5G applications. In a demonstrated design example, the proposed hardware architecture is mainly based on 16-parallel radix-2 processing engines. An 8192-point Polar encoder is designed and synthesized with TSMC 40-nm CMOS technology, operating at clock frequency of 10.0GHz and delivering total throughput of 160.0Gbps. The synthesized area only occupies 0.045mm2and consumes 413.8mW.