FPGA Implementation of 2-D DCT for JPEG Image Compression
R. N. Uma, Rajiv Gandhi · 2011
Abstract — Data (image) compression is the reduction or elimination of redundancy in data representation in order to achieve reduction in storage and communication cost. Many algorithms and VLSI architectures for the fast computation of DCT have been proposed [10,11,12]. For the fast computation of 2-D DCT, the conventional approach is the row-column method. This method requires 2N 1-D DCT’s for the computation of NxN DCT. For hardware parallel implementation using the conventional approach, a complicated matrix transposition architecture and 2N 1-D DCT modules is required which increases the area as well as delay. Thus for more efficient computation or parallel implementation of the 2-D DCT, the algorithm that work directly on the 2-D DCT is the direct polynomial approach [13] in which the number of multiplications is reduced to 50 to 75% of the conventional approach and the number of 1-D DCT required will be N so area minimization can be achieved. This paper presents a linear, highly pipelined direct polynomial fast 2-D DCT algorithm hardware implementation in which the number of multiplication is reduced to 50% of the conventional row-column approach. The coding is simulated using Xilinx 9.1 ISE synthesized using Spartan II. The 1-D and 2-D DCT implementation is done using 18-bit floating point adders, subtractors and multipliers [15]. The DCT processor saves hardware using module reusability concept and achieves high performance. The chip of 8x8 DCT processor is fabricated in a 180 nm CMOS technology. Power analysis is analyzed using CADENCE tool.