A High-Performance, Hierarchical Decoupled Architecture
Stephen P. Crago, Apoorv Srivastava, Kevin Obenland · 1996
This paper presents a novel, high-performance decoupled architecture called the HiDISC 1 (Hierarchical Decoupled Instruction Stream Computer). The HiDISC provides high performance for loop-based scientific programs by exploiting instruction-level parallelism and improving memory system peformance by providing decoupled prefetching. In this paper, we present the HiDISC architeture, a sample program to show how the architecture works, and simulation results for nine scientific benchmarks and one symbolic benchmark. The performance advantage of the HiDISC architecture increases as the miss penalty gets larger relative to processor cycles, making it an attractive architecture as the difference between processor speed and DRAM speed grows exponentially. 1.