Quick Review on Multiplication Algorithm for Enhancing Efficiency of
Irshad Khan, Sunil Shah, Vinod M. Kapse · 2015
This review work is devoted for seeking speed efficient Multiply Accumulate Unit. As we know that MAC Unit is a digital co-processor which can performs multiply then accumulate operation. MAC Unit is the heart of digital signal processors to perform various sophisticated tasks that includes FFT, DFT, resolving various complex equations and Convolution etc. apart from this it is also used in various other configurations such as IIR, FIR etc. Every digital domain based technology depends upon the operations performed by MAC Unit either partially or whole. Speed is the most prominent factor of processor and controllers being used recently. To meet this major concern of “speed” we need particular high speed MAC. That’s why it is highly required to design high speed MAC, which can enhance the efficiency of those modules which lies upon the operations performed by MAC. The speed of MAC greatly depends upon the speed of multiplier. At algorithmic and structural level there are so many multiplication algorithms exist now-a-days. After a thorough study and proper analysis we have seen that Vedic multiplication technique is the best algorithm that gives much better result in comparison to others in terms of speed. Further we have analyzed different existing Vedic multiplication hardware, and compared those with respect to speed. And found that the Vedic multiplier with Carry Save Adder gives better outcome. Then we have proposed that multiplier for the MAC unit design. This proposed MAC Unit is able to perform different arithmetic operations at high speed. All sub-modules in the MAC unit has been designed in combinatorial form. And integrated in the final module, in which we have provided the reset and clock functionality to have better control on the circuitry.