Granularity of Microprocessor Thermal Management: A Technical Report
Karthik Sankaranarayanan, Wei Huang, Mircea R. Stan, Hossein Haj‐Hariri, Robert J. Ribando, Kevin Skadron · 2009
Process technology scaling, poor supply voltage scaling and the resultant exponential increase in power density have made temperature a first-class design constraint in today�s microprocessors. An interesting question in the context of thermal management and multi-core architectures is about the correct size granularity of thermal management. It is known that the silicon substrate acts as a spatial low-pass filter for temperature. This means that if blocks with very high power density are small enough (for e.g., if they are below a �cut-off� size), they do not cause hot spots. This paper investigates this phenomenon analytically and presents a discussion through three microarchitectural examples. First is a thermal study of a many-core architecture which illustrates the thermal benefit of many small cores as opposed to a few large cores. This study also explores the effect of local vs. global thermal management. Second is an investigation of whether high aspect ratio sub-blocks such as cache lines can become hot spots due to pathological code behaviour. Third is an exploration of thermal sensor accuracy as a function of the number of sensors and a characterization of two sensor interpolation schemes as a means to reduce sensor errors.