A Reconfigurable and Scalable FPGA Architecture for Bilateral Filtering
Swapnil Deelip Dabhade, G. N. Rathna, Kunal N. Chaudhury · IEEE Transactions on Industrial Electronics · 2017
Bilateral filter is an edge-preserving smoother that has applications in image processing, computer vision, and computational photography. In the past, fieldprogrammable gate array (FPGA) implementations of the filter have been proposed that can achieve high throughput using parallelization and pipelining. An inherent limitation with direct implementations is that their complexity scales as O(ω2) with the filter width ω. In this paper, we propose an FPGA implementation of a fast bilateral filter that requires just O(1) operations for any arbitrary ω. The attractive feature of the FPGA implementation is that it is both scalable and reconfigurable. To the best of our knowledge, this is the first scalable FPGA implementation of the bilateral filter. As an application, we use the FPGA implementation for image denoising.