Comparative Analysis of Different Topologies Based on Network-on-chip Architectures
Mridula Agarwal, Rupesh Dubey, Nitin Kumar Jain, Deepak Raghuvanshi · 2013
As the integration density and complexity of the system-on-Chip (SOC) increases, the conventional interconnects are not suitable to fulfil the demands. The application of traditional network technologies in the form of Network-on-Chip is a possible solution. NoC design space has numerous variables. As an improved topology is selected complexities decrease and power-efficiency increases. In this paper, the main research field in Network-on-chip design focussing on optimized topology design is analyzed. The simulation is modelled using a conventional network simulator tool ns-2, in which by selecting proposed Topology 35.7 % reduction in traversing the longest path is observed.