A Fastest RISC Processor using Convolution Method
J. Sravana, C. Srihari, Mohd Khadir · International Journal of Engineering and Technology · 2017
The guideline set comprises of Logical, Numerous calculations have been configuration with a specific end goal to fulfill an enhanced the execution of the channels by utilizing the convolution outline.The engineering of the proposed RISC CPU is a uniform 32-bit guideline organize, single cycle nonpipelined processor.It has stack/store engineering, where the operations might be performed on registers, and not on memory areas.It takes after the traditional von-Neumann design with only one regular memory transport for both directions and information.An aggregate of 27 guidelines are composed in beginning advancement venture of the processor.Immediate, Jump, Load, store and HALT kind of direction.The joined points of interest RISC processor, for example, rapid, low power, region proficient and operation-particular outline conceivable outcomes have been dissected.In this paper we have actualized 32 bit RISC processor to perform round convolution at various modules of RISC processor like execute unit alongside ALU, Instruction get alongside guideline memory, decipher unit, resistor unit, information memory has been executed.The execution time to perform 4 bit round convolution is observed to be 270 ns.The execution time to execute the direction is observed to be 5 ns.In our paper, 3200 LUTs and 320 rationale components are utilized to execute 32 bit RISC processor which is observed to be territory effective when contrasted with different plans.