Design and Implementation of Reversible Multiplier using optimum TG Full Adder
Nekkanti Gowthami, K. Srilakshmi · IOSR Journal of Electronics and Communication Engineering · 2017
The reversible logic has received great attention in last few years due to their ability to reduce the power dissipation which is the main requirement in low power VLSI design.Multipliers are widely used in DSP for calculation of FFT, convolution, to perform MAC operation, and in microprocessors to perform ALU related operations.This paper proposes a 16X16 reversible multiplier using Toffoli gate Full adder which can multiply two 16-bit numbers.It is based on the two concepts, the partial products are generated in parallel using Toffoli gates, and the addition of partial products is carried out by using reversible full adder designed with modified TG gate.The designed multiplier is faster and has low hardware complexity.In addition to that the designed reversible multiplier is better than the existing counterparts in terms of power consumption, delay, Garbage inputs, outputs, and quantum cost.The designed 16-bit multiplier is modeled using Verilog HDL and functionality is verified with Xilinx Vivado 2016.2.