3D Discrete Wavelet Transform VLSI Architecture for Image Processing
Malay Ranjan Tripathy, Kapil Sachdeva, Rachid Talhi · 2009
In this paper, we propose an improved version of lifting based 3D Discrete Wavelet Transform (DWT) VLSI architecture which uses bi-orthogonal 9/7 fllter processing. This is implemented in FPGA by using VHDL codes. The lifting based DWT architecture has the advantage of lower computational complexities transforming signals with extension and regular data ∞ow. This is suitable for VLSI implementation. It uses a cascade combination of three 1-D wavelet transform along with a set of in-chip memory bufiers between the stages. These units are simulated, synthesized and optimized for Spartan-II FPGA chips using Active-HDL Version 7.2 design tools. The timing analysis tools of this (Active-HDL), reports the frequency above 100MHz and ensures 100% hardware utilization.