Triple-Phase Watermarking for Reusable IP Core Protection During Architecture Synthesis
Anirban Sengupta, Dipanjan Roy, Saraju P. Mohanty · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2017
Reusable intellectual property (IP) cores used in the consumer electronic devices, representing years of valuable investment, need protection against threats such as piracy and illegal claim of ownership. This paper introduces a novel 7-variable signature encoding driven triple-phase watermarking methodology during high level synthesis (HLS)/architectural synthesis for IP core protection of vendor rights. The proposed approach is extremely robust against external threats as it involves vendor signature comprising of 7-variable combination embedded through three independent phases of HLS. This paper is the first work in the HLS literature that presents a triple-phase watermarking process during HLS compared to single phase watermarking techniques so far. The proposed approach incurs zero delay overhead and minimal hardware overhead while embedding as well as yields average cost reductions of 7.38% and 6.25% compared to two similar approaches. Further, the proposed triple-phase watermark approach achieves a lower Pc value by ~3.2× 1027times in magnitude compared to similar approaches. Additionally, the proposed approach is 3.4 ×1043and 2.8 ×1019times more tamper tolerant than similar approaches.