Automatic Assertion Generation for Simulation, Formal Verification and Emulation
Tong Zhang, Daniel G. Saab, Jacob A. Abraham · 2017
Verification is a critical step in the Integrated Circuit (IC) design process. In order to verify a design, a set of assertions based on the design, is generated. The design is checked, either using simulation or formal tools, to make sure that the design does not violate any of the generated assertions. If any of the assertions is violated, then a design bug is detected. The quality of the verification is directly connected to the set of assertions and how much of the design functionality they cover. In this paper, we propose a method to automatically generate a set of high-quality design assertions. The method is based on the design description and on Automatic Test Pattern Generation (ATPG). The proposed method generates design assertions that cover 100% of the design input space and could span multiple clock cycles. In our experiment, we generated properties/assertions for a USB2.0 model from OpenCores. These assertions are compact and provide 100% input space coverage of each target node.