Experiences with High-Level Design and Modelling of Digital Systems
Stephen J. Sangwine · International Journal of Electrical Engineering Education · 1995
Experiences with high-level design and modelling of digital systems Design and modelling of digital systems has been taught at the University of Reading for six years, using Silvar-Lisco HELIX and lately IEEE Standard VHDL hardware description languages. Three exercises have been used throughout this time. These are: modelling of a multiplier-accumulator, design and modelling of a transversal filter, and specification-level modelling of a FIFO.