A 200MHz 0.65fJ/(Bit·Search)1.152kb pipeline content addressable memory in 28nm CMOS
Federico Fary, Luca Mangiagalli, Alessandra Pipino, Federica Resta, Marcello De Matteis, Andrea Baschirotto · 2017
In this paper a complete design of a Content Addressable Memory (CAM) in bulk-CMOS 28nm technology is presented. The CAM has 64×18 bit resolution, operates at 200MHz and exploits the low power pipeline searching algorithm. Dedicated circuital solutions have been adopted to mitigate the well-known issues in CMOS 28nm-bulk technology (like higher sensitivity to Process-Voltage-Temperature variations, increased gate serie resistance, very low supply voltage vs. threshold voltage, etc). This allows to take advantage of the larger transition frequency available in nm-range technologies and the lower parasitic capacitances. Simulation results (based on post-layout extracted schematic) have been carried out, validating this way the hereby proposed CAM design. Overall average power consumption is 153μW, corresponding to 0.65fJ/(Bit·Search), one of the higher Figure-of-Merit comparing with similar CAM architectures available in literature. Total area occupancy for 1.152kb resolution is 0.015mm2.