SSTL Based Energy Efficient FIFO Design for High Performance Processor of Portable Devices
Abhay Saxena, Sanjeev Kumar Sharma, Pragya Agarwal, Chandrashekhar Patel · International Journal of Engineering and Technology · 2017
Now days green computing is major research area in the computer science field, where we want to reduce the total power consumption of our device by applying different techniques .Having this concern we have designed our FIFO (First In First Out) circuit and calculated its total power dissipation at different-different families of SSTL with frequency scaling techniques.In this technique we used following (20 GHz, 40GHz, 60 GHz and 80 GHz ) frequency range.In our work first we have worked with SSTL12 and found that when we scaled down the frequency from 80 GHz to 20 GHz 71.55% reduction in total IO power.In second we have worked with SSTL15 and got 74.02% of reduction in total IO power when we reduced frequency from 80 GHz to 20 GHz.In last we worked with SSTL18_I and SSTL18_II and found 74.29% and 74.28% of reduction in total power respectively, when we scaled down the frequency from 80 GHz to 20 GHz.We have designed our FIFO on 28 nm kintex-7 FPGA family Keyword-SSTL IO standard, Low Power, Energy Efficient, 28 nm FPGA, FIFO