Implementation of highly efficient sorting algorithm for median filtering using FPGA Spartan 6
Vidya P Korakoppa, Mohana, H. V. Ravish Aradhya · 2017
Reducing the noise content in an image is the important factor in image processing and its applications. Some of the noises which cause a serious degradation in the image quality are multiplicative noise, salt and pepper noise, impulse noise, gaussian noise, additive noise etc. Among these, salt and pepper noise can be eliminated using median filtering techniques. Sorting techniques have been beneficial for median filtering. In this paper a highly efficient optimized sorting algorithm is implemented for median filter. Median filter is used to calculate the median of set of pixel values of a window. To compare the same column pixel values, data is acquired from FPGA parallely. The adjacent median filter results are saved temporarily using D flip-flops. This method increases the efficiency of execution by reducing the comparisons from 21 to 13 and significantly increases 40% efficiency. Sorting algorithm is implemented using FPGA Spartan 6 LX45. It is cost efficient and also power efficient since it consumes half the power compared to earlier Spartan families.