Design of SHA-1 & SHA-2 MIPS processor using FPGA
Safaa S. Omran, Laith F. Jumma · 2017
According to the wide developments in the area of communications, there is a demand for secure system for data transmissions. In this paper, a Hash system SHA-1 and SHA-2 Processor is designed using Xilinx Spartan-3AN and interfaced with keyboard and Video Graphics Array (VGA) Display. The implementation of the processor is done by using MIPS (Microprocessor without Interlocked Pipelines) single cycle by choosing a certain number of instructions that was necessary to invoke the SHA-1, SHA-224 and SHA-256 algorithm. A keyboard in interfaced with the Xilinx Spartan-3AN kit, to enable the user to enter the data and the result is shown on a VGA Display.