An efficient test technique to prevent scan-based side-channel attacks
Satyadev Ahlawat, Darshit Vaghani, Virendra Pal Singh · 2017
Almost every complex circuit today employs scan-based Design-for-Testability (DFT) architecture to enhance controllability and observability for every flip-flop in the design, thereby improve the testability. However, the DFT structure can also be exploited to mount side-channel attacks to retrieve the secret key stored in a cryptographic chip, thus compromising its security. In this paper, we propose a new secure scan test architecture which isolates the encryption key whenever the cryptographic chip is switched to test mode. The encryption key remains isolated during the whole scan test process. It also clears the last functional states of the security sensitive scan cells as soon as the scan test mode is activated. The proposed secure scan test approach is capable of exercising all kinds of conventional stuck-at and timing test. The proposed approach has minimal hardware overhead and it is capable of preventing existing scan-based side channel attacks.