DESIGN AND IMPLEMENTATION OF DOUBLE PRECISION FLOATING POINT ADDITION/SUBTRACTION UNIT
P.Sri Dorayya, K.B.S.D. Sarma · IJITR International Journal of Innovative Technology and Research - IJITR International Journal of Innovative Technology and Research · 2014
The floating point is a method of representing an approximation of a real number for performing calculations in any digital system. Over the years, a variety of floating-point representations have been used in computers. However, since the 1990s, the most commonly encountered representation is that defined by the IEEE 754 Standard. This paper presents an efficient implementation of double precision floating point addition/subtraction unit using verilog HDL. Results have been successfully simulated using Xilinx ISE and observed the area, timing and power report.